mainboard/gigabyte_ga-g41m-es2l: Add new mainboard supportg41

This provides SerialICE shell support for Gigabyte GA-G41M-ES2L

Change-Id: Ia91d1a030215c977fea15d8424fb34c7f20ba6fc
Signed-off-by: Damien Zammit <damien@zamaudio.com>

3 files changed, 90 insertions, 0 deletions

diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig
index 6f8df67..b232d93 100644
--- a/SerialICE/Kconfig
+++ b/SerialICE/Kconfig
@@ -79,6 +79,9 @@ config BOARD_COMMELL_LV_672
 config BOARD_DELL_S1850
 	bool "Dell PowerEdge S1850"
 
+config BOARD_GIGABYTE_GA_G41M_ES2L
+	bool "Gigabyte GA-G41M-ES2L"
+
 config BOARD_HP_DL165_G6
 	bool "HP DL165 G6"
 
@@ -176,6 +179,7 @@ config BOARD_INIT
 	default "commell_lv_672.c" if BOARD_COMMELL_LV_672
 	default "jetway_nf81_t56n_lf.c" if BOARD_JETWAY_NF81_T56N_LF
 	default "lenovo_x60.c" if BOARD_LENOVO_X60
+	default "gigabyte_ga-g41m-es2l.c" if BOARD_GIGABYTE_GA_G41M_ES2L
 
 config SOUTHBRIDGE_INIT
 	string
diff --git a/SerialICE/mainboard/gigabyte_ga-g41m-es2l.c b/SerialICE/mainboard/gigabyte_ga-g41m-es2l.c
new file mode 100644
index 0000000..d59b116
--- /dev/null
+++ b/SerialICE/mainboard/gigabyte_ga-g41m-es2l.c
@@ -0,0 +1,72 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "config.h"
+
+const char boardname[33]="Gigabyte GA-G41M-ES2L           ";
+
+/* Hardware specific functions */
+
+#define RCBA	0xfed1c000
+#define   GCS	0x3410
+#define RCBA32(x) *((volatile u32 *)(RCBA + x))
+
+static void southbridge_init(void)
+{
+	u16 reg16;
+	u32 reg32;
+
+	// Set up RCBA
+	pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1);
+
+	// Disable Serial IRQ
+	pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0x00);
+	// Set COM1 decode range
+	pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010);
+	// Enable COM1
+	pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x140d);
+
+	// Disable watchdog and route port 80 to LPC
+	RCBA32(GCS) = (RCBA32(GCS) | 0x20) & ~0x4;
+}
+
+static void superio_init(u8 cfg_port, u8 com_port)
+{
+	pnp_enter_ext_func_mode_ite(cfg_port);
+
+	// Stop reboot
+	pnp_set_logical_device(cfg_port, 0x07);
+	pnp_write_register(cfg_port, 0xef, 0x7e);
+
+	// Configure COM Port
+	pnp_set_logical_device(cfg_port, com_port);
+	pnp_set_enable(cfg_port, 0);
+	pnp_set_iobase0(cfg_port, 0x3f8);
+	pnp_set_irq0(cfg_port, 4);
+	pnp_set_enable(cfg_port, 1);
+
+	pnp_exit_ext_func_mode_ite(cfg_port);
+}
+
+static void chipset_init(void)
+{
+	southbridge_init();
+	superio_init(0x2e, 1);
+}
+
diff --git a/SerialICE/simba/chipset/intel_bars.lua b/SerialICE/simba/chipset/intel_bars.lua
index 63feb23..5353b0b 100644
--- a/SerialICE/simba/chipset/intel_bars.lua
+++ b/SerialICE/simba/chipset/intel_bars.lua
@@ -84,6 +84,20 @@ function i945_pcie_bar(f, action)
 	end
 end
 
+dev_x4x = {
+	pci_dev = pci_bdf(0,0,0,0),
+	name = "4 Series",
+	bar = {},
+}
+
+function northbridge_x4x()
+	add_mem_bar(dev_x4x, 0x40, "EPBAR", 4*1024)
+	add_mem_bar(dev_x4x, 0x48, "MCHBAR", 16*1024)
+	add_mem_bar(dev_x4x, 0x60, "DMIBAR", 4*1024)
+	add_mem_bar(dev_x4x, 0x40, "EPBAR", 4*1024)
+	pci_cfg32_hook(dev_x4x, 0x60, "PCI", i945_pcie_bar)
+end
+
 dev_i945 = {
 	pci_dev = pci_bdf(0,0,0,0),
 	name = "i945",