From 29e424aa30867d53bfec555c4db1df8d810d4181 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Sat, 1 Nov 2014 13:06:00 +1100 Subject: ga-b75m-d3h: Add new Intel mainboard This provides support for Gigabyte GA-B75M-D3H mainboard. Signed-off-by: Damien Zammit --- SerialICE/Kconfig | 10 +++ SerialICE/mainboard/gigabyte_ga_b75m_d3h.c | 27 ++++++++ SerialICE/serialice.ld | 10 +-- SerialICE/southbridge/intel-bd82x6x.c | 44 ++++++++++++ SerialICE/superio/ite-it8728f.c | 105 +++++++++++++++++++++++++++++ 5 files changed, 191 insertions(+), 5 deletions(-) create mode 100644 SerialICE/mainboard/gigabyte_ga_b75m_d3h.c create mode 100644 SerialICE/southbridge/intel-bd82x6x.c create mode 100644 SerialICE/superio/ite-it8728f.c diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index b384928..fb01a06 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -79,6 +79,9 @@ config BOARD_COMMELL_LV_672 config BOARD_DELL_S1850 bool "Dell PowerEdge S1850" +config BOARD_GIGABYTE_GA_B75M_D3H + bool "Gigabyte GA-B75M-D3H" + config BOARD_HP_DL165_G6 bool "HP DL165 G6" @@ -172,18 +175,21 @@ config BOARD_INIT default "asrock_775i65g.c" if BOARD_ASROCK_775I65G default "commell_lv_672.c" if BOARD_COMMELL_LV_672 default "jetway_nf81_t56n_lf.c" if BOARD_JETWAY_NF81_T56N_LF + default "gigabyte_ga_b75m_d3h.c" if BOARD_GIGABYTE_GA_B75M_D3H config SOUTHBRIDGE_INIT string default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M default "southbridge/amd-sbxxx.c" if BOARD_ASUS_F2A85_M || BOARD_JETWAY_NF81_T56N_LF default "southbridge/amd-sbxxx.c" if BOARD_ASUS_P2_M3A3200 + default "southbridge/intel-bd82x6x.c" if BOARD_GIGABYTE_GA_B75M_D3H config SUPERIO_INIT string default "superio/ite-it8718f.c" if BOARD_ASUS_P2_M3A3200 default "superio/winbond-w83627thg.c" if BOARD_KONTRON_986LCD_M default "superio/fintek-f71869ad.c" if BOARD_JETWAY_NF81_T56N_LF + default "superio/ite-it8728f.c" if BOARD_GIGABYTE_GA_B75M_D3H choice prompt "ROM size" @@ -210,6 +216,9 @@ config ROM_2048K config ROM_4096K boolean "4096 KB" +config ROM_8192K + boolean "8192 KB" + endchoice config ROMSIZE @@ -221,6 +230,7 @@ config ROMSIZE default 0x100000 if ROM_1024K default 0x200000 if ROM_2048K default 0x400000 if ROM_4096K + default 0x800000 if ROM_8192K choice prompt "Target communication" diff --git a/SerialICE/mainboard/gigabyte_ga_b75m_d3h.c b/SerialICE/mainboard/gigabyte_ga_b75m_d3h.c new file mode 100644 index 0000000..8bf7307 --- /dev/null +++ b/SerialICE/mainboard/gigabyte_ga_b75m_d3h.c @@ -0,0 +1,27 @@ +/* + * SerialICE + * + * Copyright (C) 2014 Damien Zammit + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="Gigabyte GA-B75M-D3H "; + +static void chipset_init(void) +{ + southbridge_init(); + it8728f_gigabyte_disable_reboot(); + superio_init(); +} diff --git a/SerialICE/serialice.ld b/SerialICE/serialice.ld index f43d9f2..d71afba 100644 --- a/SerialICE/serialice.ld +++ b/SerialICE/serialice.ld @@ -20,10 +20,10 @@ OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") OUTPUT_ARCH(i386) -ALIGNED_ROMBASE = 0x100000000 - (ALIGNED_ROMSIZE); +ALIGNED_ROMBASE = 0x100000000 - (ALIGNED_ROMSIZE) - 0x500000; _ROMSIZE = (1024 * 64); -_ROMBASE = 0x100000000 - (_ROMSIZE); +_ROMBASE = 0x100000000 - (_ROMSIZE) - 0x500000; SECTIONS { @@ -40,20 +40,20 @@ SECTIONS { *(.rodata.*); } =0xff - . = 0xffffff40; + . = 0xffffff40 - 0x700000; .messages . : { *(.messages) . = 111; BYTE(0x00); } - . = 0xffffffd0; + . = 0xffffffd0 - 0x700000; .romstrap . : { *(.romstrap) } - . = 0xfffffff0; + . = 0xfffffff0 - 0x700000; .reset . : { *(.reset) . = 15; diff --git a/SerialICE/southbridge/intel-bd82x6x.c b/SerialICE/southbridge/intel-bd82x6x.c new file mode 100644 index 0000000..069fc94 --- /dev/null +++ b/SerialICE/southbridge/intel-bd82x6x.c @@ -0,0 +1,44 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * 2014 Damien Zammit + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This initializes Intel's bd82x6x that + * o the Super IO is accessible, + * o legacy serial port I/O ports are decoded, + */ + +#include "config.h" + +static void southbridge_init(void) +{ + /* Set the value for PCI command register. */ + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x04), 0x000f); + + /* Enable Serial IRQ */ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), + (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + + /* Enable LPC decode */ + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), + (1 << 12) | (1 << 13) | (1 << 0)); + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x10); + + //pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + //pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); +} diff --git a/SerialICE/superio/ite-it8728f.c b/SerialICE/superio/ite-it8728f.c new file mode 100644 index 0000000..457db8b --- /dev/null +++ b/SerialICE/superio/ite-it8728f.c @@ -0,0 +1,105 @@ +/* + * SerialICE + * + * Copyright (C) 2006 Uwe Hermann + * 2009 coresystems GmbH + * 2014 Patrick Georgi + * 2014 Damien Zammit + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define IT8728F_SP1 0x01 /* Com1 */ +#define IT8728F_SP2 0x02 /* Com2 */ + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define IT8728F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8728F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8728F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ +#define IT8728F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8728F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ + +#define IT8728F_LDN_INDEX_GPIO 0x07 /* GPIO LDN index */ + +static void it8728f_sio_write(char ldn, char index, char value) +{ + outb(IT8728F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +static void it8728f_enter_conf(void) +{ + u16 port = SIO_BASE; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void it8728f_exit_conf(void) +{ + it8728f_sio_write(0x00, IT8728F_CONFIG_REG_CC, 0x02); +} + +/* Select 24MHz CLKIN (48MHz default). */ +static void it8728f_24mhz_clkin(void) +{ + it8728f_enter_conf(); + it8728f_sio_write(0x00, IT8728F_CONFIG_REG_CLOCKSEL, 0x1); + it8728f_exit_conf(); +} + +void it8728f_gigabyte_disable_reboot(void) +{ + it8728f_enter_conf(); + it8728f_sio_write(IT8728F_LDN_INDEX_GPIO, 0xef, 0x7e); /* magic */ + it8728f_sio_write(IT8728F_LDN_INDEX_GPIO, 0x72, 0x20); /* watchdog */ + it8728f_sio_write(IT8728F_LDN_INDEX_GPIO, 0x73, 0x00); /* watchdog */ + it8728f_exit_conf(); +} + +/* Enable the serial port(s). */ +static void superio_init(void) +{ + /* (1) Enter the configuration state (MB PnP mode). */ + it8728f_enter_conf(); + + /* (2) Modify the data of configuration registers. */ + + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + + /* it8728f_sio_write(0x00, IT8728F_CONFIG_REG_CONFIGSEL, 0x00); */ + + /* Enable serial port(s). */ + it8728f_sio_write(IT8728F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8728f_sio_write(IT8728F_SP2, 0x30, 0x1); /* Serial port 2 */ + + /* Clear software suspend mode (clear bit 0). */ + it8728f_sio_write(0x00, IT8728F_CONFIG_REG_SWSUSP, 0x00); + + /* (3) Exit the configuration state (MB PnP mode). */ + it8728f_exit_conf(); +} -- cgit v1.2.3