new board: ASUS P2-M3A3200

Adapted IT8718F early init from coreboot

Change-Id: I2c32659be40c5ff47bd13cd27b1c1e10e7a34092
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5421
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>

3 files changed, 127 insertions, 0 deletions

diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig
index 328950e..1a3a78c 100644
--- a/SerialICE/Kconfig
+++ b/SerialICE/Kconfig
@@ -33,6 +33,9 @@ config BOARD_QEMU_X86
 config BOARD_AMD_SERENGETI_CHEETAH
 	bool "AMD Serengeti Cheetah (SimNOW)"
 
+config BOARD_ASUS_P2_M3A3200
+	bool "ASUS Pundit P2-M3A3200"
+
 config BOARD_KONTRON_986LCD_M
 	bool "Kontron 986LCD-M/mITX"
 
@@ -140,6 +143,7 @@ config BOARD_INIT
 	string
 	default "qemu-x86.c" if BOARD_QEMU_X86
 	default "amd_serengeti-cheetah.c" if BOARD_AMD_SERENGETI_CHEETAH
+	default "asus_p2-m3a3200.c" if BOARD_ASUS_P2_M3A3200
 	default "kontron_986lcd-m.c" if BOARD_KONTRON_986LCD_M
 	default "roda_rk886ex.c" if BOARD_RODA_RK886EX
 	default "intel_d94x.c" if BOARD_INTEL_D945GCLF || BOARD_INTEL_D945GNT || BOARD_INTEL_D946GZIS
@@ -173,9 +177,11 @@ config SOUTHBRIDGE_INIT
 	string
 	default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M
 	default "southbridge/amd-sbxxx.c" if BOARD_ASUS_F2A85_M || BOARD_JETWAY_NF81_T56N_LF
+	default "southbridge/amd-sbxxx.c" if BOARD_ASUS_P2_M3A3200
 
 config SUPERIO_INIT
 	string
+	default "superio/ite-it8718f.c" if BOARD_ASUS_P2_M3A3200
 	default "superio/winbond-w83627thg.c" if BOARD_KONTRON_986LCD_M
 	default "superio/fintek-f71869ad.c" if BOARD_JETWAY_NF81_T56N_LF
 
diff --git a/SerialICE/mainboard/asus_p2-m3a3200.c b/SerialICE/mainboard/asus_p2-m3a3200.c
new file mode 100644
index 0000000..fa233a6
--- /dev/null
+++ b/SerialICE/mainboard/asus_p2-m3a3200.c
@@ -0,0 +1,27 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Arne Georg Gleditsch <arne.gleditsch@numascale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+const char boardname[33]="ASUS Pundit P2-M3A3200          ";
+
+static void chipset_init(void)
+{
+	southbridge_init();
+	superio_init();
+}
diff --git a/SerialICE/superio/ite-it8718f.c b/SerialICE/superio/ite-it8718f.c
new file mode 100644
index 0000000..2659532
--- /dev/null
+++ b/SerialICE/superio/ite-it8718f.c
@@ -0,0 +1,94 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ *               2009 coresystems GmbH
+ *               2014 Patrick Georgi
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define IT8718F_SP1  0x01 /* Com1 */
+#define IT8718F_SP2  0x02 /* Com2 */
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE                     0x2e
+#define SIO_INDEX                    SIO_BASE
+#define SIO_DATA                     (SIO_BASE + 1)
+
+/* Global configuration registers. */
+#define IT8718F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
+#define IT8718F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
+#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8718F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
+#define IT8718F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
+
+static void it8718f_sio_write(char ldn, char index, char value)
+{
+	outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
+	outb(ldn, SIO_DATA);
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+static void it8718f_enter_conf(void)
+{
+	u16 port = SIO_BASE;
+
+	outb(0x87, port);
+	outb(0x01, port);
+	outb(0x55, port);
+	outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8718f_exit_conf(void)
+{
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
+}
+
+/* Select 24MHz CLKIN (48MHz default). */
+static void it8718f_24mhz_clkin(void)
+{
+	it8718f_enter_conf();
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
+	it8718f_exit_conf();
+}
+
+/* Enable the serial port(s). */
+static void superio_init(void)
+{
+	/* (1) Enter the configuration state (MB PnP mode). */
+	it8718f_enter_conf();
+
+	/* (2) Modify the data of configuration registers. */
+
+	/*
+	 * Select the chip to configure (if there's more than one).
+	 * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+	 * If this register is not written, both chips are configured.
+	 */
+
+	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
+
+	/* Enable serial port(s). */
+	it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */
+	it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */
+
+	/* Clear software suspend mode (clear bit 0). */
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00);
+
+	/* (3) Exit the configuration state (MB PnP mode). */
+	it8718f_exit_conf();
+}
+