diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-03-06 20:00:11 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-11 18:56:01 +0100 |
| commit | 14d052638246f5bc14f96f10d5ec8a07eef9091b (patch) | |
| tree | 989c947bcad82c4b3a2bfc568970640317ab1403 | |
| parent | 171629643a17091ef1710825ba7fe38626c5a892 (diff) | |
Fix variable MTRR filter
Separate this from the MSR fallback filter.
This filter is not enabled by default and was actually
broken because it did not check correctly for the MSR index.
Change-Id: I83caabe38070bf45a534585f1243bc2fe9f0c724
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2596
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | SerialICE/simba/cpu.lua | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/SerialICE/simba/cpu.lua b/SerialICE/simba/cpu.lua index 22ccb33..6dad741 100644 --- a/SerialICE/simba/cpu.lua +++ b/SerialICE/simba/cpu.lua @@ -2,11 +2,14 @@ -- CPU MSR filters function var_mtrr_post(f, action) - local addr = action.rin.ecx local hi = action.rin.edx local lo = action.rin.eax + if not action.write then + return true + end + if addr % 2 == 0 then mt = lo % 0x100 if mt == 0 then memtype = "Uncacheable" @@ -25,8 +28,32 @@ function var_mtrr_post(f, action) end printk(f, action, "Set MTRR %x mask to %08x.%08x (%s)\n", (addr - 0x200) / 2, hi, bit32.band(lo, 0xfffff000), valid) end + return true +end + +function mtrr_pre(f, action) + local addr = action.rin.ecx + if addr >= 0x200 and addr < 0x210 then + return handle_action(f, action) + end + return false end +function mtrr_post(f, action) + local addr = action.rin.ecx + if addr >= 0x200 and addr < 0x210 then + return var_mtrr_post(f, action) + end + return false +end + +filter_mtrr = { + name = "MTRR", + pre = mtrr_pre, + post = mtrr_post, + hide = true, +} + function cpumsr_pre(f, action) return handle_action(f, action) end @@ -35,9 +62,6 @@ function cpumsr_post(f, action) if action.write then printk(f, action, "[%08x] <= %08x.%08x\n", action.rin.ecx, action.rin.edx, action.rin.eax) - if action.addr >= 0x200 and action.addr < 0x210 then - var_mtrr_post(f, action) - end else printk(f, action, "[%08x] => %08x.%08x\n", action.rin.ecx, action.rout.edx, action.rout.eax) |