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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-07-22 16:00:34 -0500 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-07-23 11:54:29 +0200 |
| commit | 076492f67909311f34da2772bf229e74e1026fa0 (patch) | |
| tree | f209e2d3c47f0fd8474674ec96e9cd9d22410ca9 | |
| parent | 28b0d82d9a203bbe8e042abfd470d0cba8152e9c (diff) | |
VX900: Fix decoding of southbridge MMIO BAR
Change-Id: I94ef658fb90e0c36a038e4f87a0b25e444af7e40
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3799
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
| -rw-r--r-- | SerialICE/simba/chipset/via_bars.lua | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/SerialICE/simba/chipset/via_bars.lua b/SerialICE/simba/chipset/via_bars.lua index 7868535..acb34ed 100644 --- a/SerialICE/simba/chipset/via_bars.lua +++ b/SerialICE/simba/chipset/via_bars.lua @@ -1,15 +1,18 @@ -function sb_pcie_bar(dev, reg, base) - local baseaddr = bit32.lshift(base, 16) - local size = 64*1024 +function sb_mmio_bar(f, action) + -- This MMIO space is used for SPI and CEC control + f.dev.mmio.name = "SB_MMIO" + f.dev.mmio.val = bit32.lshift(bit32.band(action.data, 0xfff0), 8) + f.dev.mmio.size = 0x10000 - pcie_mm_cfg_bar(baseaddr, size) + generic_mmio_bar(f.dev.mmio) end dev_sb = { pci_dev = pci_bdf(0,0x11,0,0), name = "sb", bar = {}, + mmio = { f = nil }, } function nb_pcie_bar(dev, reg, base) @@ -25,6 +28,6 @@ dev_nb = { } function northbridge_vx900() - pci_cfg16_hook(dev_sb, 0xbd, "SB_PCI", sb_pcie_bar) + pci_cfg32_hook(dev_sb, 0xbc, "SB_MMIO", sb_mmio_bar) pci_cfg32_hook(dev_nb, 0x0, "NB_PCI", nb_pcie_bar) end |