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| author | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2020-11-29 17:00:19 +0100 |
|---|---|---|
| committer | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2020-11-29 17:00:19 +0100 |
| commit | a9daf62fea26392c9050b5db3b110a7b5f8ea4c7 (patch) | |
| tree | 7d5cde9f4ad4060c7b9bdb835374c2e30e18d7ba | |
| parent | 261eb7f1ade265bb359609a796715fa06f4d32fd (diff) | |
x86: Fix initial control word
The value in fp_state_alloc was actually an oldie, the value in fpinit
was the expected one nowadays.
* i386/i386/fpu.c (CWD_DEFAULT): Set to 0x37f.
| -rw-r--r-- | i386/i386/fpu.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/i386/i386/fpu.c b/i386/i386/fpu.c index 365187ee..ee8cadcd 100644 --- a/i386/i386/fpu.c +++ b/i386/i386/fpu.c @@ -79,9 +79,14 @@ static unsigned long mxcsr_feature_mask = 0xffffffff; /* Always AND user-provide /* Default FPU configuration */ #define MXCSR_DEFAULT 0x1f80 -#define CWD_DEFAULT ((0x037f \ - & ~(FPC_IM|FPC_ZM|FPC_OM|FPC_PC)) \ - | (FPC_PC_64|FPC_IC_AFF)) +#define CWD_DEFAULT (FPC_PC_64 | /* 64bit precision */ \ + FPC_RC_RN | /* round-to-nearest */ \ + FPC_ZE | /* Suppress zero-divide */ \ + FPC_OE | /* and overflow */ \ + FPC_UE | /* underflow */ \ + FPC_IE | /* Allow NaNQs and +-INF */ \ + FPC_DE | /* Allow denorms as operands */ \ + FPC_PE) /* No trap for precision loss */ \ #if NCPUS == 1 volatile thread_t fp_thread = THREAD_NULL; |