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2023-01-02model_16_init: Add cpu model 0x700f01bring-back-agesaDamien Zammit
Change-Id: I5cdc4a5840797a3155dc1cc345d47d0dfc514c2b Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01WIP: mb/hp/t620: Add new board HP T620Damien Zammit
This is the diff applied to the previous commit to change the biostar/a68n_5200 port into support for new board: HP T620 thin client. This work was done during a coreboot hacking party! Board is AMD Fam16kb with laptop ram. It has a socketed SOIC8 chip and SIO accessible serial, making it a good target for testing/maintaining this platform. coreboot console works over serial COMA by default. Board is fanless, so no need for fan control. TESTED: Boots SeaBIOS 1.14.0 and to debian 11, NIC works, serial works. Have had 120 days of uptime with this particular port and no issues. Missing: - Audio verb table (deleted) - PIRQs could be wrong (copied from other board) - ACPI could be wrong (copied from other board) Caveat: Without VGA BIOS rom there are no displays. VGA ROM was extracted from /dev/mem @ 0xC0000 on a running system and one DP was tested to work. NB: Since bringing back AGESA code with resource allocator v4 and parallel mp init, this board no longer boots due to some kind of CBFS alignment issue, I need some help to figure this out. cbfs: This image contains the following sections that can be manipulated with this tool: 'RW_MRC_CACHE' (size 65536, offset 0) 'COREBOOT' (CBFS, size 8322560, offset 66048) It is possible to perform either the write action or the CBFS add/remove actions on every section listed above. To see the image's read-only sections as well, rerun with the -w option. CBFSPRINT coreboot.rom FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs_master_header 0x0 cbfs header 32 none config 0x80 raw 2327 LZMA (6878 decompressed) revision 0xa00 raw 717 none build_info 0xd00 raw 89 none fallback/dsdt.aml 0xd80 raw 5950 none cmos_layout.bin 0x2500 cmos_layout 616 none fallback/postcar 0x27c0 stage 21688 none payload_config 0x7cc0 raw 1621 none payload_revision 0x8340 raw 235 none (empty) 0x8480 null 31012 none apu/amdfw 0xfdc0 raw 69632 none fallback/romstage 0x20e00 stage 386080 none fallback/ramstage 0x7f2c0 stage 125180 LZMA (283964 decompressed) pci1002,9837.rom 0x9dc40 optionrom 65536 none fallback/payload 0xadc80 simple elf 72756 none (empty) 0xbf900 null 7524836 none bootblock 0x7ecb00 bootblock 12992 none ... Built hp/t620 (T620) tail of coreboot log: ... [INFO ] CBFS: Found 'pci1002,9837.rom' @0x9dc40 size 0x10000 in mcache @0x5ffdd2a4 [NOTE ] Mapping PCI device 10029837 to 10029830 [DEBUG] In CBFS, ROM address for PCI: 00:01.0 = 0xff8ade6c [DEBUG] Copying VBIOS image from 0xff8ade6c [DEBUG] ACPI: * VFCT at 5fe9d420 [DEBUG] ACPI: added table 8/32, length now 68 [DEBUG] ACPI: * HPET [DEBUG] ACPI: added table 9/32, length now 72 [INFO ] ACPI: done. [DEBUG] ACPI tables: 89808 bytes. [DEBUG] smbios_write_tables: 5fe8e000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.18-1385-g5be491174b' [DEBUG] SMBIOS tables: 529 bytes. [DEBUG] Writing table forward entry at 0x00000500 [EMERG] ASSERTION ERROR: file 'src/lib/coreboot_table.c', line 80 [EMERG] ASSERTION ERROR: file 'src/lib/coreboot_table.c', line 428 Change-Id: Ieaa724f393194f762d55263a74b04c9fde93e53f Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01mb/hp/t620: Add clone of biostar/a68n-5200Damien Zammit
HP T620 was ported to coreboot based on the biostar/a68n-5200 port. This commit is a direct clone of the previous board, with the name changed to make it pass jenkins, and extra SPDX headers on empty files. Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01amd smm: Add missing amd_mp_ops_no_smm struct and tie in to fam16kbDamien Zammit
Change-Id: I6b159433c111525aed1451acfd2540eab8fdc8f7 Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01agesa/common: Add missing VOIDDamien Zammit
Change-Id: Ifd2339ef69e14ffa48c2b652a76b4dce5b35277b Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01cpu/amd/smm: Remove dead codeDamien Zammit
Change-Id: I9c2d3f23be45c8ae76609e0e650864e4ad7a5ad3 Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01nb/amd/agesa/family16kb: Enable RESOURCE_ALLOCATOR_V4Damien Zammit
Change-Id: Id02f119b786c19cd3fc185cae7f1abcd2daa2b67 Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01cpu/amd/family16: Use parallel mp initArthur Heymans
This now computes an MTRR solution based on coreboots allocation and always uses that solution over the one set by AGESA. Syncing MSR is now done in sipi_vector.S. Change-Id: If3326c5fbd278f8f974d5408e16440e3b56b1b44 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-01Revert "{cpu/nb}/amd/family16: Remove platform"Damien Zammit
This reverts commit 49af4f7f9197e559b2c7142129441679bb1d24a2. Change-Id: I78d41a626228baed81b467e284268c9a5cc57aca Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01Revert "vendorcode/amd/agesa/family16: Drop unused platform"Damien Zammit
This reverts commit 7036ded25d3a051902862e2a7bdfe15916f0951d. Change-Id: I1782946f293c866c9a88f2a7824b0fe7dc4e6297 Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01Revert "vendorcode/amd/agesa: Drop unused common code"Damien Zammit
This reverts commit 0f12381083fdfc7bb3e6f3b2ac5cd6247506c543. Change-Id: I2726767999b10e1fa3527a67719a4f7c1b93eb5c Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01Revert "cpu/amd/agesa: Remove leftover code"Damien Zammit
This reverts commit 81a4fefce223ba358310aec2d988484202c176e2. Change-Id: Icf2b15a158fc4a22e07d0051e4f23dd804a4a148 Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01Revert "nb/amd/agesa: Remove leftover code"Damien Zammit
This reverts commit 1a010236cf922fc28cfb36b604bdf17a9ea3cb82. Change-Id: If26ce3136f809d5b0714fc344ddff1f8df3789bc Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01Revert "sb/amd: Remove dropped platforms"Damien Zammit
This reverts commit 03a6ccd20d9bb54e3a009269b8e454ee8a2e3051. Change-Id: I72d8ac5ceddf46f2b3f0c95c0f122c661ec7e888 Signed-off-by: Damien Zammit <damien@zamaudio.com>
2023-01-01apollolake/include/soc/meminit.h: Add missing stdboolElyes Haouas
stdbool is added through types.h file. Change-Id: I317faf322a7e73b706724802d99815ab50e655e2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-31security/intel/stm/StmPlatformResource.c: Fix typo on "threads"Elyes HAOUAS
Change-Id: Id57a9c689d5fa35cf1b4df9c37b12dd95cb9ef23 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-31mb/google/brya/var/gladios: Update audio codec i2c timingKevin Chiu
Adjust audio codec i2c timing to 399 kHz. BUG=b:262959586 TEST=FW_NAME=gladios emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I2f621e3af39fb40ab270c9de35d51dd43147b8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-31Enable VBOOT_VBNV_FLASH for SOC_INTEL_BRASWELLYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for boards using SOC_INTEL_BRASWELL. Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for CPU_INTEL_HASWELL, SOC_INTEL_BRASWELL and others (see [2]). However, there seems to be no particular reason on those platforms. We've dropped the config for haswell. Now do the same for SOC_INTEL_BRASWELL, so that VBOOT_VBNV_FLASH can be enabled. VBOOT_VBNV_FLASH is enabled for the following boards: - facebook/fbg1701: A 0x2000 RW_NVRAM region is allocated, with the FW_MAIN_A(CBFS) size reduced by 0x2000. - google/cyan, intel/strago: Repurpose RW_UNUSED as RW_NVRAM. [1] https://issuetracker.google.com/issues/235293589 [2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 ("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config") BUG=b:235293589 TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected) TEST=./util/abuild/abuild -x -t GOOGLE_CYAN -a TEST=./util/abuild/abuild -x -t INTEL_STRAGO -a Change-Id: I46542c2887b254f59245f20b8642b023a7871708 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-31mb/facebook/fbg1701: Enlarge COREBOOT region for VBOOT by 64kBYu-Ping Wu
When VBOOT is enabled, the COREBOOT region (of size 0x09B000) is not large enough. Therefore, adjust vboot-rw.fmd (which is used only with VBOOT) layout by moving 0x10000 space from FW_MAIN_A(CBFS) region to COREBOOT(CBFS) region. TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected) Change-Id: I1bc0d6981b873ca631cc4cc0720ab212700a65aa Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-31mb/google/rambi: Drop ChromeOS supportYu-Ping Wu
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS [1] and replace with VBOOT_VBNV_FLASH. However, the rambi's CAR is too small for early flash access in romstage: /usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: Cache as RAM area is too full /usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: section .car.mrc_var VMA [00000000fe008000,00000000fe00ffff] overlaps section .car.data VMA [00000000fe000000,00000000fe008787] make: *** [src/arch/x86/Makefile.inc:194: coreboot-builds/GOOGLE_RAMBI/cbfs/fallback/romstage.debug] Error 1 More precisely, DCACHE_RAM_SIZE is 0x8000, and the current .car.data size is 0x76c0. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is unselected, then the _bss region will increase by 0x10c8 bytes (for global variables such as `elog_mirror_buf` and `sfg`), so that .car.data will exceed 0x8000. Since rambi has reached its AUE (2021-09-01), disable MAINBOARD_HAS_CHROMEOS and VBOOT configs. [1] https://issuetracker.google.com/issues/235293589 BUG=b:235293589 TEST=./util/abuild/abuild -t GOOGLE_RAMBI -a TEST=./util/abuild/abuild -x -t GOOGLE_RAMBI -a Change-Id: Id56795dd0653784b4d7141142ebef0b19a46ddc3 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71545 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-30fw_config: Fix typo in documentBora Guvendik
There is no fw_config_probe_one api, change it to fw_config_probe. BUG=none TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I916713c038f72a1718be8c9d4e8e21420effbf76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-30mb/google/skyrim/var/frostflow: Update I2C setting for touchpadJohn Su
Update setting for touchpad I2C frequency. And meet touchpad i2c SPEC (380 ~ 400 kHz). BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 390.1 kHz Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ied00e43e87404489af2b570206a70b685e554b78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71564 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29{ec,mb}/system76/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ia5ae30a1ee976b8059936027b28ac56f37279217 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71516 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29mb/intel/mtlrvp: Add configuration for UART devicesHarsha B R
This patch adds below configuration for MTL-RVP UART devices, Interface -> UART0 PCI -> 0:0x1e:0 Device -> AP UART BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp ito chromeOS using subsequent patches in the train. UART logs appear on AP console. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I4702d603aa49357f4db0d18d646e536d9d81787e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70873 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-29mb/intel/mtlrvp: Configure GPIO Tier-1 GPEs for MTL-RVPHarsha B R
Configure GPIO Tier-1 GPE's that defines the route for GPE events for MTL-RVP. Configure GPE route as below, PMC_GPE0_DW0 -> GPP_B PMC_GPE0_DW1 -> GPP_D PMC_GPE0_DW2 -> GPP_E BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to ChromeOS using subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ieab95b72ade75734b0788a32566649d90acbc48a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70872 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-28coding_style: Add more guidelines on error handling, die() and assert()Julius Werner
This patch adds a new section to the coding style which codifies existing practices about how to handle errors and how to use the die() and assert() macros. Also clean up some references to Linux-specific facilities that do not exist in coreboot in the adjacent function return type guidelines, and add a small blurb of documentation to the definition of the assert() macro itself. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ice37ed9f995a56d69476e95a352209041b337284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70775 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-28src/security/vboot: Fix wrong CONFIG nameMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I2af3bc9bf9eaf258b9180da5fc5494b21764f379 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71518 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-28mb/google/brya/var/kuldax: Add wifi sar tableDavid Wu
Add wifi sar table for kuldax BUG=b:248367859 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I5ade590c739aae391e47e8bb66ee03c086e8d56e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71270 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27soc/intel/alderlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include intelblocks/gpio.h BUG=b:261778357 TEST=Able to build and boot Google/brya. Change-Id: Ia90a8ea7b4ee125657c7277e3e14018cfe5423a9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71266 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-27mb/google/brya/var/kano: Enable Fast VMode for kanoDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:252966799 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I15c3eea6ebb7f104bce0ba8cb544ecde7f488343 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVPHarsha B R
Add devicetree and GPIO configuration for MTL-RVP Changes include, 1. Add initial devicetree to support MTL-RVP board & variant 2. Add initial setup for ramstage gpio config BRANCH=none BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to chromeOS using subsequent patches in the train. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I3173c3f32b36d24467431df3652badd70efeab93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-27mb/intel/mtlrvp: Add bootblock and early gpio for MTL-RVPHarsha B R
This patch adds initial bootblock code. This also configures required GPIOs for early board initialization. 1. Add bootblock file for MTL-RVP 2. Add early gpio config for MTL-P variant in gpio.c BRANCH=none BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform to ChromeOS with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I9c0893e52036147c5f6bbfafc6d818e9d3460bed Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-27mb/google/rex: Enable PMC IPC configSubrata Banik
TEST=Able to build and boot Google/Rex. Device (PMC) { Name (_HID, "INTC1026") // _HID: Hardware ID Name (_DDN, "Intel(R) Meteor Lake IPC Controller") // _DDN: DOS Dev ice Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0B) } ... } Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I28c0153a770b36cde0653ac92d2e5ad1b8dd3449 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71268 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{superio,ec}/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I449ec5b0bbf3f24d51688efef151d3018d2848b2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71524 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mainboard/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mainboard/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{superio,ec}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I5c77b6d1e1dc1134f62dcb3e93df01dc9c2f386c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71520 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mb/google/brya/var/marasov: Add DmaProperty for ISHSubrata Banik
On Marasov, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Add DmaProperty to the ISH _DSD on Marasov. TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the IOMMU group type to "DMA". Also, device still goes to S0i3. Before: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 0 After: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 1 Change-Id: I4b65b8909c41b06852fe7771375029bd2e76e111 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71263 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27drivers/intel/ish: Add ADL-P ISH DIDSubrata Banik
This patch adds ISH ID for ADL-P to ensure dynamic ASL code is added into SSDT. With this patch: Scope (\_SB.PCI0.ISHB) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48dc6056155824239bb88eda2b0ff5bcd36ced15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71262 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27mb/google/brya/var/marasov: Remove ISH firmware-nameSubrata Banik
For marasov, the ISH main firmware will be included in the CSE region in flash instead of loading it from rootfs. So remove the ISH firmware-name. TEST=Boot to OS on Marasov UFS SKUs. Check ISH firmware is not loaded by kernel, and device still goes to S0i3. Change-Id: I278e5d403ef9515e538a527f43949e505d750bb1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71261 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com>
2022-12-26sio/winbond/w83627hf/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntaxElyes Haouas
Replace Divide (a,b,c,d) with: c = a % b d = a / b Change-Id: I0e9fdabbb4b5bd9698968cd8acb497dcde14e433 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71508 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26tree/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntaxFelix Singer
Replace `Divide (a, b, c, d)` with these instructions: c = a % b d = a / b Change-Id: I44366be5b5145a5d19f85df7a2f338866cb9c8b0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-26mb/lenovo/s230u/acpi: Replace Not(a, b) with ASL 2.0 syntaxFelix Singer
Replace `Not (a, b)` with `b = ~a`. Change-Id: I0f18119c8e91222e59a56b8509f12c6ece6d04ce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71514 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26tree/acpi: Replace Not(a) with ASL 2.0 syntaxFelix Singer
Replace `Not (a)` with `~a`. Change-Id: I53993fb7b46b3614d18ee001323f17efacbf04c1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26drivers/pc80/vga: Add NULL check for `vga_line_write()`Subrata Banik
This patch ensures vga_line_write() returns if the argument 1 (aka output string) is NULL. TEST=Able to build and boot Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I716ce82c0afe21f7fe2f6d7bdc5229f8087242fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-26sio/acpi/pnp.asl: Replace Not(a) with ASL 2.0 syntaxElyes Haouas
Change-Id: Icbd2ab736b9fc3300ee82896c31b373fe92e1d54 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71509 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26nb/intel/ironlake/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I6af7131e151700569d50e8bc42bfaeb7a58fa7d3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71507 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26nb/intel/sandybridge/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I75bc048d9e04be8d0cab25f6aad1c71d3e7a4008 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71506 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-31 23:02:01 +0000