diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2022-12-26 00:07:42 +0800 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-12-28 00:56:00 +0000 |
| commit | 872079656b9b47795e778bf86a074b7ed185327a (patch) | |
| tree | b1f833357d6697aab74db9e19adf8fdcd9dadb77 | |
| parent | d910fec9a6c925d3bf6cfaaed90f74c7095050d2 (diff) | |
mb/google/brya/var/kuldax: Add wifi sar table
Add wifi sar table for kuldax
BUG=b:248367859
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage
Change-Id: I5ade590c739aae391e47e8bb66ee03c086e8d56e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71270
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/brya/Kconfig.name | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/kuldax/variant.c | 8 |
2 files changed, 8 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 094c7ed581..8e38735215 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -248,6 +248,7 @@ config BOARD_GOOGLE_MITHRAX config BOARD_GOOGLE_KULDAX bool "-> Kuldax" select BOARD_GOOGLE_BASEBOARD_BRASK + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENESYSLOGIC_GL9755 config BOARD_GOOGLE_JOXER diff --git a/src/mainboard/google/brya/variants/kuldax/variant.c b/src/mainboard/google/brya/variants/kuldax/variant.c index 04105db2ea..e9b11a639b 100644 --- a/src/mainboard/google/brya/variants/kuldax/variant.c +++ b/src/mainboard/google/brya/variants/kuldax/variant.c @@ -1,8 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <baseboard/variants.h> #include <chip.h> #include <fw_config.h> -#include <baseboard/variants.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { |